1. Technical Field
The present invention relates generally to built-in test circuits implemented in field programmable gate arrays (FPGAs), and more specifically to a method and apparatus for tracing hardware states within an FPGA.
2. Description of the Related Art
Field Programmable Gate Arrays (FPGAs) provide flexibility in implementing logic designs by allowing reconfiguration of logical circuits via download of binary information. Recent developments in FPGA technology have led to the availability of FPGAs with over 100,000 gates or more within a single Integrated Circuit (IC) package.
FPGAs are frequently used in dedicated peripherals attached to computer systems, particularly in graphics applications, where their high speed and reconfigurability yield an advantage. For example, graphics display electronics and printer graphics electronics that convert bit-plane information into serial data streams have been implemented using the FPGA technology. Because microprocessors and microcontrollers are not efficient for the high-speed serialization/de-serialization of bitstreams, dedicated very-large-scale integrated (VLSI) circuits are used for this purpose. The VLSI circuits are typically gate arrays, having a mask that is designed once and never modified until another version of the VLSI circuit is designed and verified. VLSI circuits have a high non-recurring engineering (NRE) cost for mask design and production tooling. FPGAs provide an alternative solution having advantages including quick design and modification turn-around and reconfigurability.
Since the FPGA designs can be quickly modified during the design process and for version upgrades, and since alternate logic configurations may be supported, a method that matches the short design turn cycle (in many cases less than one hour) to the verification and debugging process would be desirable. It would also be desirable to allow for field debugging in cases where there may be a quick solution to a field site problem by modifying the logic, but no ready way to verify the low-level behavior of a new logic design in the field.
Due to the complexity of circuits that can be implemented in a present-day FPGA, there is a need to provide measurement of intermediate signals within the FPGA, but without using a significant number of an FPGA""s Input/Output (I/O) pins from the FPGA.
Therefore, it would be desirable to provide a method and apparatus for tracing logic states within an FPGA, and further provide for field testing and design debugging of computer peripherals using FPGAs in their implementations.
The above-mentioned objectives are achieved in a method and apparatus for tracing hardware states within functional logic using dynamically reconfigurable test circuits. One or more sets of reconfigurable test circuits are used to make measurements for debugging and troubleshooting. A particular test circuit can be selected by a software tracing program and test information may be read from the test circuit by a microcontroller or microprocessor. This information can be synchronized with software trace information, providing a unified trace history of software and hardware. The test circuits may incorporate counters, event detectors, comparators and other miscellaneous test circuits that enable design engineers or field service personnel to determine more readily the cause of problems within the functional logic or software.
The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.